Programmable logic devices (PLDs), including field-programmable gate arrays (FPGAs), are integrated circuits (ICs) that can be programmed to implement user-defined logic functions. In a typical FPGA architecture, an array of configurable logic blocks (CLBs) and a programmable interconnect structure are surrounded by a ring of programmable input/output (I/O) circuit elements. Examples include the Virtex™ II Platform FPGA from Xilinx Inc. of San Jose Calif., and the Stratix™ device architecture from Altera Corp. of San Jose, Calif.
FIG. 1 is a simplified schematic view of a conventional FPGA 48. The FPGA includes a programmable fabric 2 surrounded by an I/O ring 4. The programmable fabric 2 includes configurable logic block (CLB) columns 5, block random access memory (BRAM) columns 6, and a digital signal processing (DSP) column 7. The programmable fabric 2 further includes the programmable interconnect structure (not shown in FIG. 1) which allows the circuit elements or blocks in the programmable fabric to be interconnected with each other and with the circuit elements or blocks in the I/O ring. The I/O ring includes input and output circuit elements, for example, input/output blocks (IOBs)
As can be seen from FIG. 1 the I/O ring 4 is at the perimeter of the programmable fabric 2. Signals external to FPGA 48 can only communicate with the programmable fabric 2 via this perimeter I/O ring 4. There are a few disadvantages with this conventional arrangement. First, the total number of IOBs allowed is limited by, in effect, the circumference of the FPGA 48 rather than the area of the FPGA. Second, internal signals located in circuit elements near the center of the FPGA 48 must propagate to the perimeter via the programmable interconnect structure to exit the FPGA 48. Thus propagation delays are dependent upon distance of the circuit element to the perimeter. Third, manufacturing the FPGA 48 is complicated. The columns of mostly homogeneous circuit elements of the programmable fabric 2 must be fabricated and aligned with the circuit elements of I/O ring 4. The manufacturing problem is further exacerbated, as seen by FIG. 2 below, in that the I/O ring 4 has a few heterogeneous elements.
FIG. 2 is a more detailed diagram of another conventional FPGA having various CLB, IOB, and BRAM/multiplier tiles. The word “tile” is an area comprising a) circuitry with one or more programmable functions, including memory, or fixed non-programmable circuitry, and b) programmable interconnections. The CLB tiles 12 are laid out in a two-dimensional array. In this example, each CLB tile includes a portion of the configurable interconnect structure such that at least part of the interconnect structure for the FPGA 50 is formed by the various portions of the many CLBs when the CLB tiles are placed together on the FPGA. Also illustrated are block random memory/multiplier (BRAM/Mult) tiles 13.
In order to provide input/output circuitry for interfacing the FPGA 50 to external logic, IOB tiles 14 are provided along each of the four sides (top, bottom, left, right) of the FPGA. In this particular design, an input/output interconnect tile (IOI tile) is used to couple each pair of IOB tiles to a CLB tile. Reference numeral 11 points to one such IOI tile. IOI tile 11 is disposed between the two IOB tiles to its right and the CLB tile to its left.
In the example of FIG. 2, clock management (e.g., digital clock management or DCM) circuitry is fitted into the areas 15, 21, 22 and 27 above and below the leftmost and rightmost columns of BRAM/multiplier tiles. The other rightmost columns of BRAM/multiplier tiles have T-shaped multi-giga bit (MGT) transceiver tiles 28–35. The corner areas 16–19 of the FPGA 50 may be used to accommodate other miscellaneous circuitry. This miscellaneous circuitry may, for example, include configuration logic, encryption/decryption logic, global clock driver circuitry, a system performance monitor, and boundary scan circuitry.
For additional information on a tiled FPGA floorplan see U.S. Pat. No. 5,914,616 issued Jun. 22, 1999 by Young et. al. and U.S. Pat. No. 6,204,689 B1, issued Mar. 20, 2001, by Andrew K. Percy, et. al., both of which are incorporated by reference herein.
FIG. 2 has the same disadvantages listed for FIG. 1. In addition, modification of the layout of FIG. 2 is difficult. For example, addition of another column of BRAM/Mult tiles requires significant changes in both the programmable fabric as well as the I/O ring. Another example of a disadvantage, is that adding one or more DSP columns may require an entire new layout.
Thus there is need for techniques that minimize and/or eliminate the above-described disadvantages.